1. Field of the Invention
The present invention relates to an array of nitride read only memory (NROM) cells. More particularly, the present invention relates to a NROM memory array in which each cell has two independently controllable gates.
2. Description of Related Art
A conventional NROM cell comprises a P-type substrate on which is formed an oxide/nitride/oxide (ONO) stacked layer structure, with the silicon nitride layer serving as an electron trapping layer. A control gate structure of a conducting polycrystalline layer is formed on the silicon oxide/silicon nitride/silicon oxide layer. An N+ source region and an N+ drain region are located in the substrate on either side to the gate structure.
The conventional NROM cell can store two bits of information, one bit of information being stored as the presence or absence of negative charges in the trapping layer at the side of the source region and one bit of information being stored as the presence or absence of negative charges in the trapping layer at the side of the drain region. The bit information at the source and the drain regions is separately read by detecting the presence of absence of current flowing between the source and the drain when appropriate voltages are applied to the gate, the source and the drain. However, in reading one of the two bits of data in the conventional NROM cell, the magnitude of the current that travels between the source and the drain regions may be affected by the presence or absence of the other bit of data. This is called the second-bit effect. The presence of the second-bit effect makes less reliable, the reading of a state of the cell.
In addition to the second bit effect, when NROM cells are configured in an array, a so called array effect may occur, which results in an incorrect reading of the state of a cell. The array effect is caused by leakage currents from adjacent memory cells. Accordingly, it would be desirable for an NROM cell to have the capability of storing two bits of data where the presence of absence of one bit of the data does not influence the detection of the state of the other bit of data and where leakage currents from adjacent cells in an array which could effect the reliability of detecting the state of a cell are not generated.